// Verilog test fixture created from schematic U:\VGA\VGA_sch.sch - Sun Dec 07 14:14:09 2008

`timescale 1ns / 1ps

module VGA_sch_VGA_sch_sch_tb();

// Inputs
   reg clock;
   reg reset;
	reg wEn;
	reg [15:0] writeData;

// Output
   wire [5:0] VGAout;
   wire vSyncOut;
   wire hSyncOut;
   //wire read;

// Bidirs
	integer i;
// Instantiate the UUT
   VGA_sch UUT (
		.VGAout(VGAout), 
		.vSyncOut(vSyncOut), 
		.hSyncOut(hSyncOut),  
		.clock(clock),
		.wEn(wEn),
		.writeData(writeData),
		.reset(reset)
   );
// Initialize Inputs
      initial begin
		clock = 0;
		reset = 0;
		wEn = 0;
		writeData = 15'd0;
   #100
	for(i = 0; i < 21; i = i + 1)
	begin
	#1
		clock <= ~clock;
		if(i == 0)
			reset <= 1;
		else if(i == 20)
			reset <= 0;
	end
	end
always
#1 clock = ~clock;
endmodule
